A New Embedded Measurement Structure for eDRAM Capacitor

Submitted on behalf of EDAA (http://www.edaa.com/)International audienceThe embedded DRAM (eDRAM) is more and more used in System On Chip (SOC). The integration of the DRAM capacitor process into a logic process is challenging to get satisfactory yields. The specific process of DRAM capacitor and the low capacitance value (~30F) of this device induce problems of process monitoring and failure analysis. We propose a new test structure to measure the capacitance value of each DRAM cell capacitor in a DRAM array. This concept has been validated by simulation on a 0.18µm eDRAM technology

Self-consistent physical modeling of set/reset operations in unipolar resistive-switching memories

International audienceThis letter deals with a self-consistent physical model for set/reset operations involved in unipolar resistive switching memories integrating a transition metal oxide. In this model, set operation is described in terms of a local electrochemical reduction of the oxide leading to the formation of metallic conductive filaments. Beside, reset operation relies on the thermally-assisted destruction of the formed metallic filaments by Joule heating effect. An excellent agreement is demonstrated with numerous published experimental data suggesting that this model can be confidently implemented into circuit simulators for design purpose. Memory devices based on resistive switching materials are currently pointed out as promising candidates to replace conventional non-volatile memory devices based on charge-storage beyond 2x nm-technological nodes. 1 In particular, devices integrating a transition metal oxide (so-called TMO) such as NiO, TiO 2 , ZnO or Cu x O, are of growing interest due to their simple Metal/Insulator/Metal (MIM) structure, oxides compatible with complementary metal-oxide-semiconductor technology and low process temperature. 2 So far, in TMO-based memory devices, the unipolar switching between low resistance state (LRS) and high resistance state (HRS) is explained in terms of creation/destruction of conductive filaments within the oxide. 3,4 Waser et al. 5 explained that set, i.e. the transition from HRS to LRS, originates from a local reduction reaction leading to the creation of metallic conductive filaments (CF). During reset, local dissipation of Joule power enhances the thermally activated diffusion of defects and/or of different atomic species constituting the CF combined with a local oxidation process. 6,7 Based on this phenomenological description , several models for reset were reported in Refs. 8–10 but very few offer a model for set. 11 Furthermore, it has to be stressed that there is currently no complete model taking into account both set and reset operations that could be easily implemented in circuit simulators for design purpose. In this context, this paper proposes a self-consistent physical model accounting for both set/reset operations in NiO-based unipolar resistive switching devices. After uncovering the theoretical background and the set of relevant physical parameters, the model is confronted to quasi-static and dynamic experimental data from literature. Fig

Embracing the Unreliability of Memory Devices for Neuromorphic Computing

The emergence of resistive non-volatile memories opens the way to highly energy-efficient computation near- or in-memory. However, this type of computation is not compatible with conventional ECC, and has to deal with device unreliability. Inspired by the architecture of animal brains, we present a manufactured differential hybrid CMOS/RRAM memory architecture suitable for neural network implementation that functions without formal ECC. We also show that using low-energy but error-prone programming conditions only slightly reduces network accuracy

SITARe: a fast simulation tool for the analysis of disruptive effects on electronics

This paper is devoted to an exhaustive presentation of a fast computation numerical tool, dedicated to the simulation of transient currents induced by stochastic events in microelectronic devices. This is a part of a numerical platform, SITARe, combining a spice simulator with the semi-analytical model presented here. The paper describes the theoretical model, the calibration. An instance of application illustrates the ability of the tool

RRAM Crossbar Arrays for Storage Class Memory Applications : Throughput and Density Considerations

As more and more high density memories are required to satisfy the Internet of Things ecosystem, academics and industrials are looking for an intermediate solution to fill the gap between DRAM and Flash NAND in the memory hierarchy. The emergence of Resistive Switching Technologies (RRAM) proposes a potential solution to this demand for fast, low cost, high density and non-volatile memory. However, nowadays transistor-less RRAM-based architectures, such as Crosspoint, suffers of several issues such as sneakpath, IRdrop and periphery overhead. In this work, we propose to explore the positioning of RRAM crosspoint memories regarding DRAM and NAND in terms of density and write throughput. We present several design guidelines then show that for the optimal RRAM crosspoint architecture (2-layers with common bitline), massively multiple bank write is the solution to optimize density and write throughput to around 20-100Gbit/cm2 and 200-500MB/s respectively for 32 to 64 parallel access

Switching event detection and self-termination programming circuit for energy efficient ReRAM memory arrays

Energy efficiency remains a challenge for the design of non-volatile resistive memories (ReRAMs) arrays. This memory technology suffers from intrinsic variability in switching speed, programming voltages and resistance levels. The programming conditions of memory elements (e.g. pulse widths and amplitudes) must cover the tail bits to avoid programming failures. Switching time of ReRAMs shows wide distributions. Therefore, fast cells are subjects for electrical stress after their switching and energy waste since programming currents are typically large for this technology (tens of µA). In this paper, we present a Write Termination (WT) circuit to stop the programming operation when the switching event occurs in the selected memory element. The proposed design is sensitive to current variations that take place when the memory element switches between two different resistance states (LRS and HRS). This WT scheme reduces the power consumption by 97+%, 93+% and 65+% during Forming, RESET and SET operations respectively. Our estimations show that area efficiency of 70% for a memory array is achievable when the presented WT circuit is integrated in near-memory peripheries. The demonstrated WT circuit is suitable for different ReRAM technologies with small overhead penalty and shows robustness against CMOS and ReRAM variabilities

Test et diagnostic de défauts dans les interconnexions métalliques des circuits numériques par infrastructures "IP"

La problématique de ce sujet se focalise sur les interconnexions métalliques intervenant dans les circuits numériques, de façon à répondre, d'une part, à l'augmentation des produits logiques, mais d'autre part, à plus de la majorité des étapes du procédé de fabrication. La complexité des circuits et du procédé de fabrication associée à l'amélioration des rendements nécessite le développement de nouveaux outils de test et de diagnostic afin de favoriser la rapidité et la rentabilité du test et des analyses. Ces outils conservent les avantages d'une corrélation entre la conception, la fabrication et le test, tout en s'orientant vers les technologies de systèmes sur puces. Ainsi, l'utilisation de structures sous forme d'infrastructures "IP" est inévitable. Notre approche de test et de diagnostic de défauts s'est basée sur l'obtention de signatures électriques représentatives des divers états de défaillances. Ensuite, plusieurs simulations ont permis de créer ou générer dynamiquement un dictionnaire de fautes pour le diagnostic de défaillances. Une première infrastructure "IP", dont la structure matricielle redimensionnable permet une insertion comme PCM ou comme bloc "IP", diagnostique les défauts critiques dans les interconnexions par l'utilisation d'outils d'analyse et de visualisation des signatures de défauts. L'architecture d'une seconde infrastructure "IP", basée sur la fusion de cellules mémoires "SRAM" et d'oscillateurs en anneau, permet le diagnostic de défauts critiques et paramétriques globaux mais aussi la caractérisation de défauts paramétriques locaux par l'utilisation de modèles mathématiques de signatures électriques obtenues par transformée de FourierAIX-MARSEILLE1-BU Sci.St Charles (130552104) / SudocSudocFranceF